1. Chips to Startup (C2S) Programme at 100 + Institutions including Academia, R&D Organization, Startup& MSMEs. Details here.
2. Design Linked Incentive (DLI) Scheme at 100 start-ups, MSMEs and domestic companies. Details here.
3. Fabless Chip Design Incubator (FabCI) at IIT Hyderabad. Details here.
4. “Microprocessor Development Programme” by C-DAC, IIT-Madras and IIT-Bombay.
5. “Security and Edge Intelligence hardware extensions for SHAKTI Based Compute Environment” by IIT Madras
6. “Design and Development of NavIC Receiver” at SAMEER-Mumbai, IIT-Mumbai, IIT-Madras, IIT-Jodhpur, IIST-Thiruvananthapuram.
8. M.Des programme/Executive development programme in Electronics Product Design by IIT Guwahati
9. Special Manpower Development Programme (SMDP)- M. Tech. in Electronic Product Design and Skill Development by IISc Bangalore.
1. “Design of a Parallel Processor for NPL Application” at IIT-Kanpur
2. “A study to microcells Transport process heading to the Development of Cooling Study for Electronics Competent” at IIT-Kharagpur
3. “Design of an Embedded Processor for Smart Camera System” at CEERI Pilani and IIT-Delhi
4. “Cart-Effective Tools for Relating of High-Performance Circuit Interconnection in Nan metric Technology Regime” at IIM-Calcutta, Kolkata
5. “System Jet Based Cooling for High Heat Flu3 Electronics Components A Novel Approach” at IIT-Bombay
6. “Design of Reconfigurable Application Specific Institution-Set Processor (RASIP) for Software Defined Reds (SDR).” at IIT-Roorkee
7. “Investigations of CMOS Device Technology for Strain – Engineered MOSFETS using CAD” at IIT-Kharagpur
8. “Reconfigurable Computational Structures for CMPs/MP-SoCs Platforms” at IISc Bangalore
9. “Design to Development of system level Reconfiguration Computing system” at CEERI Pilani
10. “Development-Fabrication of ASIC Productionisation of Digital Programmable Hearing Aid (DPHA) and its Deployment” at CDAC Thiruvananthapuram
11. “Centre for Analog Mixed Signal Integrated Circuit Design” at IIT-Madras
12. “Centre for Analog Mixed Signal Integrated Circuits” at IISc Bangalore
13. “Design of Mixed Signal Circuits for Instrumentation Applications” at CEERI Pilani
14. “Design of the Parallel Processor for NLP Applications” at IIT-Kanpur
15. “Design Automation of Analog VLSI” at IIT-Kharagpur
16. “Strategies for Reducing Power Consumption during VLSI Circuit Testing” at IIT-Kharagpur
17. “Development of Advanced processing stabilities in LTCC” at CMET Pune
18. “Development of MEMS Based Integrated Micro Gas Sensor for VOCs and Pollutant Gases” at CEERI Pilani
19. “Analog Mixed Signal and RFIC Development and Test for Biomedical Applications” at IIT-Bombay
20. “Feasibility Steady and preparation of dart proposal for Indian Microprocessor” at CDAC Bangalore
21. “Low Power CODEC for Digitally Programmable Meaning Aids” at IIT-Madras
22. “Thermal Aware Testing of VLSI Circuits and Systems” at IIT-Kharagpur
23. “Design and Implementation of Low Power Analog Front End Modules for Wireless Sensor Networks” at NIT Tiruchirappalli
24. “Virtualization and Security Aware Multi-Core Architecture- By Supercomputer Education and Research Centre” at IISc Bangalore
25. “Design and Characterization of CMOS Base Millimetre-Wave Components for 60 GHz Integrated Broadband Transceivers” at IISc Bangalore
26. “Setting up of Facilities for Fabrications of MEMS Devices” at Tezpur University
27. “Technical Evaluation and Preparation of a proposal for Design of an India Microprocessor” at CDAC Thiruvananthapuram
28. “Low-Temperature and Low-Pressure CU-CU Fine Pitch Bonding for Vertical (3-D) Integration” at IIT Hyderabad
29. “Bluetooth Transceiver RFIC” at IIT-Madras
30. “Design and Development of MEMS Based SoC of Wide Band Energy Harvesting for Cellular Application” at IIT-Delhi.
31. “Special Manpower Development Programme for Chips to System Design” at 60 academic institutes spread across the country including IITs, NITs, IIITs, IISc and other engineering colleges. Details here.
32. Swadeshi Microprocessor Challenge- Innovate Solutions for #Aatmanirbhar Bharat.Details here.